A salient feature of sequential logic circuits is memory. The output of a sequential logic circuit depends not only on the current values of applied input signals but also on the past circuit state, e.g. the sequence of previously applied input signals.
Sequential logic circuits can be asynchronous or synchronous. Asynchronous sequential circuits respond immediately to changes in input signals, yielding changed output signals. However, unequal propagation delays in asynchronous circuits can lead to hazards and race conditions.
To overcome these difficulties in asynchronous circuits, synchronous circuits are employed in which signals are latched into registers in response to regular clock pulses. The speed of synchronous circuits, however, is constrained by the period of the clock cycles, which depends on the propagation delays of logic blocks and registers.
For example, FIG. 3 depicts a synchronous circuit including two blocks of combinational logic: a first logic block 302 for computing a function "F" based on "N" inputs I.sub.1 -I.sub.N and a second logic block 306 for computing a function "G" based on "M" inputs F.sub.1 -F.sub.M. The circuit also includes three registers 300, 304, and 308 for latching bits at the beginning of each clock cycle.
When "N" bits are latched in register 300 at the beginning of a clock cycle, they are applied as inputs I.sub.1 -I.sub.N to the first logic block 302 after some propagation delay for the register 300. The first logic block 302 computes the function "F" on the input bits and produces therefrom "M" bits of output F.sub.1 -F.sub.M. These output bits F.sub.1 -F.sub.M are applied to a register 304, which latches those bits in response to the clock signal at the next clock cycle.
After the bits F.sub.1 -F.sub.M are latched by register 304, they are applied the second logic block 306. In response, the second logic block 306 computes the function "G" based on the bits F.sub.1 -F.sub.M and produces therefrom "L" bits of output G.sub.1 -G.sub.L. These output bits G.sub.1 -G.sub.L are applied to register 306 and latched in response to the clock signal at the next clock cycle. Thus, the computation of functions "F" and "G" takes two clock cycles to complete.
Since conventional practice tends to use a common clock signal throughout a digital circuit, the clock period is set slower than the slowest logic block. Since most functions in the circuit are faster than the slowest logic block, there is much time wasted in the digital circuit waiting for the common clock signal.
In the example, let us assume that registers 300, 304, and 308 have a propagation delay of 7 ns, the first logic block 302 has a propagation delay of 21 ns, and the second logic block 306 has a propagation delay of 28 ns. Thus, the computation in the first clock cycle needs at least 28 ns to complete (7 ns for the register 300 to latch+21 ns for first logic block 302). The computation in the second clock cycle, on the other hand, requires at least 35 ns to complete before the data is ready to be latched by register 308 (7 ns for the register 304+28 ns for the second logic block 306). Since registers 300, 304, and 308 share a common clock signal, the clock period is set to 35 ns. Thus, the total time taken to perform the two computations, i.e. two clock cycles, is 70 ns. However, 7 ns of the first clock period of 35 ns was spent waiting for the next clock cycle. Therefore, digital functions are conventionally cascaded at the speed of the common clock, which is slower than cascading at the speed of most of the functions themselves.